Titlebook: VLSI-SoC: Forward-Looking Trends in IC and Systems Design; 18th IFIP WG 10.5/IE José L. Ayala,David Atienza Alonso,Ricardo Reis Conference

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Tri-mode Operation for Noise Reduction and Data Preservation in Low-Leakage Multi-Threshold CMOS Ci suppression during activation events. A threshold voltage tuning methodology is presented to further alleviate the mode transition noise with smaller sleep transistors in MTCMOS circuits. Alternative applications of tri-mode MTCMOS for data preservation and leakage power reduction in idle memory elements are also discussed.

蟄伏

Smart Camera System-on-Chip Architecture for Real-Time Brush Based Interactive Painting Systems,me. A dedicated SoC hardware implementation avoids unnecessary latency delays caused by PC based architectures, that require communication-, PC and GPU frame-buffer delays, thereby considerably enhancing the interactivity experience. The system is prototyped on an FPGA.

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Conference proceedings 2012he current trend toward increasing chip integration and technology process advancements bringing about stimulating new challenges both at the physical and system-design levels, as well as in the test of theses systems.

簡(jiǎn)略

Self-Timed Rings: A Promising Solution for Generating High-Speed High-Resolution Low-Phase Noise Cle high-speed multi-phase outputs and we suggest a design flow for designing low-phase noise self-timed ring oscillators. A test chip has been designed and fabricated in STMicroelectonics CMOS65nm technology to verify the theoretical claims and validate the simulation results.

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Design and Optimization of a Digital Baseband Receiver ASIC for GSM/EDGE,esign trade-offs are highlighted to prove the efficiency of the implemented 2.5G multi-mode architecture. The ASIC in 0.13 .m CMOS technology occupies 1.0 mm. and dissipates only 1.3 mW in fastest EDGE data transmission mode.

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