| 書目名稱 | Test Resource Partitioning for System-on-a-Chip | | 編輯 | Krishnendu Chakrabarty,Vikram Iyengar,Anshuman Cha | | 視頻video | http://file.papertrans.cn/904/903330/903330.mp4 | | 叢書名稱 | Frontiers in Electronic Testing | | 圖書封面 |  | | 描述 | .Test Resource Partitioning for System-on-a-Chip. is about test resource partitioning and optimization techniques for plug-and-play system-on-a-chip (SOC) test automation. Plug-and-play refers to the paradigm in which core-to-core interfaces as well as core-to-SOC logic interfaces are standardized, such that cores can be easily plugged into "virtual sockets" on the SOC design, and core tests can be plugged into the SOC during test without substantial effort on the part of the system integrator. The goal of the book is to position test resource partitioning in the context of SOC test automation, as well as to generate interest and motivate research on this important topic...SOC integrated circuits composed of embedded cores are now commonplace. Nevertheless, There remain several roadblocks to rapid and efficient system integration. Test development is seen as a major bottleneck in SOC design, and test challenges are a major contributor to the widening gap between design capability and manufacturing capacity. Testing SOCs is especially challenging in the absence of standardized test structures, test automation tools, and test protocols...Test Resource Partitioning for System-on-a-Chi | | 出版日期 | Book 2002 | | 關(guān)鍵詞 | Hardware; Standard; automation; circuit; data compression; development; integrated circuit; logic; manufactu | | 版次 | 1 | | doi | https://doi.org/10.1007/978-1-4615-1113-7 | | isbn_softcover | 978-1-4613-5400-0 | | isbn_ebook | 978-1-4615-1113-7Series ISSN 0929-1296 | | issn_series | 0929-1296 | | copyright | Springer Science+Business Media New York 2002 |
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