Titlebook: System-level Test and Validation of Hardware/Software Systems; Matteo Sonza Reorda,Zebo Peng,Massimo Violante Book 2005 Springer-Verlag Lo

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Modeling Permanent Faults,d at structural level, became mandatory to constrain design quality and costs. However, as product complexity increases, the test process (including test planning, DfT and test preparation) needs to be concurrently carried out with the design process, as early as possible during the top-down phase,

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Test Generation: A Hierarchical Approach,y, on the other hand, is usually considered only when the detailed structural information of the design is available. This is mainly due to the lack of general applicability of the existing high-level test generation and design-for-test methods. In this chapter we will present an improvement of the

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Test Program Generation from High-level Microprocessor Descriptions,ing from early design phases. The methodology is based on an almost automatic tool and could be applied to generate test-programs for stand-alone microprocessor cores as well as for these embedded in systems-on-chip. The main idea is to take advantage of all possible microprocessor descriptions deli

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Tackling Concurrency and Timing Problems,ic execution. A concurrent system can perform many different correct computations for a given input sequence because the absolute order of execution is dependent on factors which cannot be known at design/compile time. Synchronization constructs are used to restrict the set of possible computations

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An Approach to System-level Design for Test,h, where the test set is assembled from pseudorandom test patterns that are generated online and deterministic test patterns that are generated offline and stored in the system. We have analyzed the aspects related to the cost calculation of such a hybrid BIST approach and will propose a test cost m

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System-level Dependability Analysis, which is made up of several .. We assume that the components, which may be designed with the support of hardware—software codesign tools, are characterized by dependability (. failure rate) parameters, which may derive from simulators of the components while they are under development, or as a resu

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Book 2005 (SOC), together with its associated manufacturing problems, represents a real challenge for designers...SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until

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