Titlebook: On-Chip Interconnect with aelite; Composable and Predi Andreas Hansson,Kees Goossens Book 2011 Springer Science+Business Media, LLC 2011 Em

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Related Work, Chapter 1. Throughout this chapter, we highlight the contributions of our proposed interconnect and how it compares to the related works. For a more detailed exposition of the key concepts, we refer back to Chapter 2.

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Conclusions and Future Work, addition, the applications have diverse requirements and behaviours and are started and stopped dynamically at run time. To reduce the design and verification complexity, it is crucial to offer a platform that enables independent implementation, verification and debugging of applications.

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2193-0155 . The book shows how these qualitative requirements are implemented in a state-of-the-art on-chip interconnect, and presents the realistic, quantitative costs.978-1-4614-2711-7978-1-4419-6865-4Series ISSN 2193-0155 Series E-ISSN 2193-0163

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Allocation,ation constraints are satisfied, and that all the use-cases fit on the given hardware resources. In this chapter, which corresponds to Step 2 in Fig. 1.8, we present an allocation algorithm that matches the application requirements with the interconnect resources.

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Book 2011but also the multi-faceted, application-driven requirements, in particular composability and predictability. The book shows how these qualitative requirements are implemented in a state-of-the-art on-chip interconnect, and presents the realistic, quantitative costs.

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