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Titlebook: Network-on-Chip Architectures; A Holistic Design Ex Chrysostomos Nicopoulos,Vijaykrishnan Narayanan,Ch Book 2010 Springer Science+Business

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書目名稱Network-on-Chip Architectures
副標題A Holistic Design Ex
編輯Chrysostomos Nicopoulos,Vijaykrishnan Narayanan,Ch
視頻videohttp://file.papertrans.cn/663/662911/662911.mp4
概述A comprehensive study of Network-on-Chip architectures for multi-core chips.Analysis of complex interplay between various design evaluation metrics.Detailed look at both macro- and micro-architectural
叢書名稱Lecture Notes in Electrical Engineering
圖書封面Titlebook: Network-on-Chip Architectures; A Holistic Design Ex Chrysostomos Nicopoulos,Vijaykrishnan Narayanan,Ch Book 2010 Springer Science+Business
描述[2]. The Cell Processor from Sony, Toshiba and IBM (STI) [3], and the Sun UltraSPARC T1 (formerly codenamed Niagara) [4] signal the growing popularity of such systems. Furthermore, Intel’s very recently announced 80-core TeraFLOP chip [5] exemplifies the irreversible march toward many-core systems with tens or even hundreds of processing elements. 1.2 The Dawn of the Communication-Centric Revolution The multi-core thrust has ushered the gradual displacement of the computati- centric design model by a more communication-centric approach [6]. The large, sophisticated monolithic modules are giving way to several smaller, simpler p- cessing elements working in tandem. This trend has led to a surge in the popularity of multi-core systems, which typically manifest themselves in two distinct incarnations: heterogeneous Multi-Processor Systems-on-Chip (MPSoC) and homogeneous Chip Multi-Processors (CMP). The SoC philosophy revolves around the technique of Platform-Based Design (PBD) [7], which advocates the reuse of Intellectual Property (IP) cores in flexible design templates that can be customized accordingly to satisfy the demands of particular implementations. The appeal of such a modul
出版日期Book 2010
關(guān)鍵詞Computer Architecture; Energy Efficiency; Fault Tolerance; Network-on-Chip; On-Chip Interconnects; integr
版次1
doihttps://doi.org/10.1007/978-90-481-3031-3
isbn_softcover978-94-007-3049-6
isbn_ebook978-90-481-3031-3Series ISSN 1876-1100 Series E-ISSN 1876-1119
issn_series 1876-1100
copyrightSpringer Science+Business Media B.V. 2010
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https://doi.org/10.1007/978-90-481-3031-3Computer Architecture; Energy Efficiency; Fault Tolerance; Network-on-Chip; On-Chip Interconnects; integr
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978-94-007-3049-6Springer Science+Business Media B.V. 2010
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1876-1100 7], which advocates the reuse of Intellectual Property (IP) cores in flexible design templates that can be customized accordingly to satisfy the demands of particular implementations. The appeal of such a modul978-94-007-3049-6978-90-481-3031-3Series ISSN 1876-1100 Series E-ISSN 1876-1119
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Chrysostomos Nicopoulos,Vijaykrishnan Narayanan,Chita R. Das
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