Titlebook: Network and Parallel Computing; 11th IFIP WG 10.3 In Ching-Hsien Hsu,Xuanhua Shi,Valentina Salapura Conference proceedings 2014 IFIP Intern

彈藥

HiNetSim: A Parallel Simulator for Large-Scale Hierarchical Direct Networksrithms. As a demonstration of HiNetSim, studies on flattened butterfly, 4D Torus and a proposed hierarchical network are given. Evaluation shows that HiNetSim achieves linear parallel speedup and is capable of simulating the network with tens of thousands nodes.

低三下四之人

Automatic Data Layout Transformation for Heterogeneous Many-Core Systemsy automated data layout transformation framework. Programmers can maintain the code in AoS style on the host, while the data layout is converted into SoA when being transferred to the device. The proposed framework streamlines the design flow and demonstrates up to 177% performance improvement.

JOT

abysmal

Multilayer Perceptron and Stacked Autoencoder for Internet Traffic Predictionr is a deep learning Stacked Autoencoder (SAE). It is shown herein how a simpler neural network model, such as the MLP, can work even better than a more complex model, such as the SAE, for Internet traffic prediction.

heirloom

APP-LRU: A New Page Replacement Method for PCM/DRAM-Based Hybrid Memory Systems detect read/write intensity for each page in the memory, and put read-intensive pages into PCM while placing write-intensive pages in DRAM. We conduct trace-driven experiments on six synthetic traces and one real OLTP trace. The results show that our proposal is able to reduce up to 5 times of migrations more than its competitors.

FID

Benchmarking the Memory Hierarchy of Modern GPUshared memory access latency. Our benchmarking results offer a better understanding on the mysterious GPU memory hierarchy, which can help in the software optimization and the modelling of GPU architectures. Our source code and experimental results are publicly available.

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