| 書(shū)目名稱 | Low Power Design with High-Level Power Estimation and Power-Aware Synthesis |
| 編輯 | Sumit Ahuja,Avinash Lakshminarayana,Sandeep Kumar |
| 視頻video | http://file.papertrans.cn/589/588796/588796.mp4 |
| 概述 | Integrates power estimation and reduction for high level synthesis, with low-power, high-level design.Shows specific techniques for ASICs as well as FPGA based SoC designs, allowing readers to evaluat |
| 圖書(shū)封面 |  |
| 描述 | This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design. |
| 出版日期 | Book 2012 |
| 關(guān)鍵詞 | Hardware Software Co-Design; High Level Synthesis; Low Power Design; Power Aware Synthesis; System Level |
| 版次 | 1 |
| doi | https://doi.org/10.1007/978-1-4614-0872-7 |
| isbn_softcover | 978-1-4899-8780-8 |
| isbn_ebook | 978-1-4614-0872-7 |
| copyright | Springer Science+Business Media, LLC 2012 |
|Archiver|手機(jī)版|小黑屋|
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