Titlebook: High Performance Computing - HiPC 2007; 14th International C Srinivas Aluru,Manish Parashar,Viktor K. Prasanna Conference proceedings 2007

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A Speed-Area Optimization of Full Search Block Matching Hardware with Applications in High-Definitioper proposes some techniques to increase the speed and reduce the area requirements of an FSBM hardware. These techniques are based on modifications of the Sum-of-Absolute-Differences (SAD) computation and the MacroBlock (MB) searching strategy. The design of an FSBM architecture based on the propos

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Evaluating ISA Support and Hardware Support for Recursive Data Layoutse row-major and column-major [3][12]. However, recursive data layouts require non-traditional address computation which involves bit-level manipulations that are not supported in current processors. As such, a number of software-based address computation techniques have been developed ranging from t

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qTLB: Looking Inside the Look-Aside Bufferor the application running on the core, due to the constant flushing of entries on context switches. Recent technologies like virtualization enable independent execution of software domains leading to performance issues because of interesting dynamics at the shared hardware resources. The advent of

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Analysis of x86 ISA Condition Codes Influence on Superscalar Executionarchitecture includes some of those characteristics. In particular, it is well know the negative impact of condition codes usage. In a coarse approximation, they can be considered responsible for a greater code coupling. Moreover, several in-depth works show that they introduce additional complexity

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Direct Coherence: Bringing Together Performance and Scalability in Shared-Memory Multiprocessors node, which must be accessed on every cache miss before any coherence action can be performed. In this work we present a new protocol that moves the role of storing up-to-date coherence information (and thus ensuring totally ordered accesses) from the home node to one of the sharing caches. Our pro

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