Titlebook: High Performance Computing for Computational Science - VECPAR 2002; 5th International Co José M. L. M. Palma,A. Augusto Sousa,Vicente Herná

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Parallel Implementation for Probabilistic Analysis of 3D Discrete Cracking in Concrete parallel vector processor (PVP). The computational strategies used for each realization, within the framework of Monte Carlo simulation, are the inexact Newton method to solve the highly nonlinear problem and element-by-element (EBE) iterative strategies considering that nonlinear behavior is restr

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High Performance Data Miningtomated data-driven techniques of extracting useful knowledge. Data mining, an important step in this process of knowledge discovery, consists of methods that discover interesting, non-trivial, and useful patterns hidden in the data [SAD+93, CHY96]. The field of data mining builds upon the ideas fro

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High Performance Computing in Electron Microscope Tomography of Complex Biological Structuresmens, with a special emphasis upon the computational perspective. Efficient iterative algorithms that are characterized by a fast convergence rate have been used to tackle the image reconstruction problem. The use of smooth basis functions provides the reconstruction algorithms with an implicit regu

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Visualization of RNA Pseudoknot Structuresules such as frame-shifting, read-through, and the initiation of translation. There exists no automatic method for drawing RNA pseudoknot structures, and thus representing RNA pseudoknots currently relies on significant amount of manual work. This paper describes the first algorithm for automaticall

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The Cactus Framework and Toolkit: Design and Applicationsemical engineering.We first motivate by example the need for such frameworks to support multi-platform, high performance applications across diverse communities. We then describe the design of the latest release of Cactus (Version 4.0) a complete rewrite of earlier versions, which enables highly mod

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Evaluating the Performance of Space Plasma Simulations Using FPGA’s (FPGAs). Although FPGA’s run at slower clock speeds than their off-the-shelf counterparts, the processing power lost in the reduced number of clock cycles per second is quickly recovered in the high degree of spatial parallelism that is achievable within the devices. We describe the development of