Titlebook: High Level Synthesis of ASICs under Timing and Synchronization Constraints; David C. Ku,Giovanni Micheli Book 1992 Springer Science+Busine

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Behavioral Transformations,teroperation parallelism in the behavior. Understanding the parallelism can give an indication of the . design synthesis can produce, assuming in the final implementation each operation is implemented by a dedicated hardware component. While this assumption may not be realistic due to area and inter

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Sequencing Graph and Resource Model, hierarchical . is used to model hardware behavior for synthesis. The hardware behavior is assumed to be synchronous and non-pipelined. As with other hardware models, both control-flow and data-flow dependencies are represented by the sequencing graph model. Its main distinction is that it uniformly

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Relative Scheduling,nstraints. Detailed timing constraints capture minimum and maximum bounds on the start time of operations; synchronization constraints model handshaking and coordination among concurrent computation threads, and are represented as operations with . execution delays.

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Resource Conflict Resolution,rce simultaneously. When all operations in the hardware model have fixed execution delays, conflict resolution becomes part of the scheduling and resource binding tasks. In particular, operations scheduled to different control steps or belonging to mutually exclusive conditional branches can share t

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Relative Control Generation,rol synthesis is important because it affects the control flow of operations and hence directly impacts the overall performance of the resulting hardware. There are many different styles of control implementation, ranging from ROM-based microprogrammed controllers [SLP88] to finite-state machines [C

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Relative Control Optimization,d either at the logic level by using a . model [MSBSV90, SDP90] or at a higher level by using a hardware model described in terms of constraints on the sequencing and timing of the operations [Wo190, DM92]. In the former case, the operations are bound to control states. This implies that the cycle-p

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Experimental Results,SIC designs were synthesized using this system, including an Ethernet coprocessor [GC91], a Digital Audio input output (DAIO) chip [LBMG89], a bi-dimensional discrete cosine transform (BDCT) chip [RM89], a decoder chip for the space telescope [Kas89], a raster line drawing design, an error-correctin

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Conclusions and Future Work,thesis approaches have primarily been targeting general-purpose processor and signal processing applications. This research focuses instead on the synthesis of ASIC designs. ASIC designs are typified by network controllers and communication modules for which system integration plays a important role