Titlebook: Evolvable Systems: From Biology to Hardware; 5th International Co AAndy M. Tyrrell,Pauline C. Haddow,Jim Torresen Conference proceedings 20

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Yvonne Thorhauer,Christoph A. Kexel that takes into account both logic and routing configurations. Experiments were run using a software model of the Xilinx Virtex FPGA. We report that using four Virtex combinational logic blocks, we were able to evolve a 100% accurate quadrature decoder finite state machine in the presence of a stuck-at-zero fault.

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A Genetic Representation for Evolutionary Fault Recovery in Virtex FPGAs that takes into account both logic and routing configurations. Experiments were run using a software model of the Xilinx Virtex FPGA. We report that using four Virtex combinational logic blocks, we were able to evolve a 100% accurate quadrature decoder finite state machine in the presence of a stuck-at-zero fault.

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A Developmental Method for Growing Graphs and Circuitsd be created that could not be evolved. It is shown that the circuit building programs are capable of correctly predicting the next circuit in a sequence of larger even parity functions. The new method however finds building specific circuits more difficult than a non-developmental method.

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A Learning, Multi-layered, Hardware Artificial Immune System Implemented upon an Embryonic Arrayonic array allows simple, robust reconfiguration to avoid the fault; as many faults as spare cells can be accommodated. The complete system, including the learning algorithm, is implemented on a Virtex FPGA. Results showing the appropriate response to different types of faults are given.

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