Titlebook: Correct Hardware Design and Verification Methods; 11th IFIP WG 10.5 Ad Tiziana Margaria,Tom Melham Conference proceedings 2001 Springer-Ver

矛盾心理

Sinusoidal Oscillators: ProblemsThe main idea of our approach is to model discretization at state level by introducing the discrete states approximating the continuous ones, and then derive a specification of the control program over discrete states. Then the control program is derived from its specification using an extension of Hoare triples to real-time.

HARP

ensemble

I-LEARN: Information Literacy for Learners-preserving RTL transformation called ., to collectively perform the same task as that of a scheduler. Violation of the transformation precondition signals an error and the sequence of RTS transformations applied so far forms a trace which can be used for debugging purposes.

圖畫文字

增減字母法

Applications of Hierarchical Verification in Model Checkingms to successfully verify a wide spectrum of large and complex circuits. This paper describes a variety of the decomposition techniques that we have used as part of a large industrial formal verification effort on the Intel Pentium? 4 (Willamette) processor.

evince

不斷的變動

Deriving Real-Time Programs from Duration Calculus SpecificationsThe main idea of our approach is to model discretization at state level by introducing the discrete states approximating the continuous ones, and then derive a specification of the control program over discrete states. Then the control program is derived from its specification using an extension of Hoare triples to real-time.

Humble

Formally-Based Design Evaluation Logic in Lotos - the ISO Language Of Temporal Ordering Specification). Relations for (strong) conformance are defined to verify a design specification against a high-level specification. Tools have been developed for automated testing and verification of conformance between an implementation and its specification.

魅力

Verification of Basic Block Schedules Using RTL Transformations-preserving RTL transformation called ., to collectively perform the same task as that of a scheduler. Violation of the transformation precondition signals an error and the sequence of RTS transformations applied so far forms a trace which can be used for debugging purposes.

Diaphragm

Parameterized Verification of the FLASH Cache Coherence Protocol by Compositional Model Checkingf assistant, a proof system based on symbolic model checking. The proof process is described step by step. The protocol model is derived from an earlier proof of the FLASH protocol, using the PVS system, allowing a direct comparison between the two methods.