Titlebook: Correct Hardware Design and Verification Methods; IFIP WG 10.2 Advance George J. Milne,Laurence Pierre Conference proceedings 1993 Springer

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A Petri Net approach for the analysis of VHDL descriptions,hniques of Petri nets. The bad behaviours that we consider concern the execution control flow of a VHDL description. This methodology works in three steps. First, a formal description in Petri Net terms of the execution control flow of a VHDL description is realized. We present the basic rules to pe

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Verification and diagnosis of digital systems by ternary reasoning,rmal verification by ternary simulation is feasible. In this paper, we demonstrate that complete verification of Finite State Machines is possible by ternary simulation. The verification vectors are derived from AND/OR trees. We also show how design error diagnosis can be performed by utilizing the

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Logic verification of incomplete functions and design error location,l circuit. For an incompletely specified function, a method to compute the corresponding 3-terminal BDD that represents the ON-set, OFF-set and DC-set, is described. Two incomplete functions are equivalent if, and only if, their 3-terminal BDDs are isomorphic. If the gate-level circuit is verified t

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A methodology for system-level design for verifiability,is paper presents a system-level design methodology that supports verification. Starting from a description in a proper subset of VHDL, a Petri Net description is obtained and used for validation purposes and for building the corresponding automaton. An efficient BDD-based tool for Process Algebra m

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Combining symbolic evaluation and object oriented approach for verifying processor-like architecture RT-level. We develop a new method which combines the extensibility and flexibility of object oriented programming paradigm and the efficiency of a specialized computer algebra system. An object oriented programming is naturally well-adapted to express the behaviour associated to each category of c

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Towards verifying large(r) systems: A strategy and an experiment,not yet feasible on a routine basis. The goal of the work discussed here is to enable the verification of large(r) real systems than currently feasible with any one of the available techniques, and to dovetail the verification methodology with the an underlying design methodology. The specific desig