Titlebook: Architecture of Computing Systems – ARCS 2018; 31st International C Mladen Berekovic,Rainer Buchty,Thilo Pionteck Conference proceedings 20

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A Hybrid Approach for Runtime Analysis Using a Cycle and Instruction Accurate Modeluating the different processor cores regarding their runtime for a certain algorithm requires simulation tools which make emulation feasible. They come in two flavors: Cycle and instruction accurate simulation. The first one offers a high accuracy regarding the estimated time but is very slow. The s

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A CAM-Free Exascalable HPC Router for?Low-Energy Communicationselements. While this problem is being addressed by designing increasingly more power-efficient processing subsystems, little effort has been put on reducing the power consumption of the interconnection network. This is precisely the objective of this work, in which we study the benefits, in terms of

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Improving the Performance of STT-MRAM LLC Through Enhanced Cache Replacement Policy area and power consumption. In this paper, we consider an emerging non volatile memory technology, namely the Spin-Transfer Torque Magnetic RAM (STT-MRAM), with a powerful cache replacement policy in order to design an efficient STT-MRAM Last-Level Cache (LLC) in terms of performance. Well-known be

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Conference proceedings 2018any, in April 2018..The 23 full papers presented in this volume were carefully reviewed and selected from 53 submissions. ARCS has always been a conference?attracting leading-edge research outcomes in Computer Architecture and Operating?Systems, including a wide spectrum of topics ranging from embed

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A Hybrid Approach for Runtime Analysis Using a Cycle and Instruction Accurate Modelecond one offers a high simulation speed but only provides a very imprecise estimation of the real runtime. This paper shows a new approach that allows to combine these kinds of simulation to increase the exactness of the estimated time while limiting the additionally required simulation time.