Titlebook: Architecture of Computing Systems - ARCS 2011; 24th International C Mladen Berekovic,William Fornaciari,Cristina Silva Conference proceedin

Apogee

Experiences with String Matching on the Fermi Architecturepaper we present an efficient implementation of the Aho-Corasick string matching algorithm on Graphic Processing Units (GPUs), showing how we progressively redesigned the algorithm and the data structures to fit on the architecture. We then evaluate the implementation on single and multiple Tesla C2

superfluous

Hyperopia

Application-Aware Power Saving for Online Transaction Processing Using Dynamic Voltage and Frequencyservers, power saving of an online transaction processing (OLTP) systems, which are major applications in data centers, is important. The OLTP system consumes relatively large amount of power because it is often equipped with a lot of computing and storage resources. Its power saving is difficult be

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Frameworks for Multi-core Architectures: A Comprehensive Evaluation Using 2D/3D Image Registrationes onto one chip. This changed also the way programs are written in order to leverage the processing power of multiple cores of the same processor. In the beginning, programmers had to divide and distribute the work by hand to the available cores and to manage threads in order to use more than one c

IDEAS

Emulating Transactional Memory on FPGA Multiprocessors We introduce two systems, integrating only off-the-shelf components, that respectively use a centralized and a distributed approach, presenting their hardware and software design. We analyze and compare these two architectures to a lock based multiprocessor prototype, discussing the trade-offs in t

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Ligament

COMA

conservative

A Dynamic Instruction Scratchpad Memory for Embedded Processors Managed by Hardwarehat every instruction will be fetched from the local, fast and timing predictable scratchpad memory. Thus, a predictable behavior is reached that eases a precise timing analysis of the system. We estimate the hardware resources required to implement the dynamic instruction scratchpad for an FPGA. An

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