Titlebook: Analog Design Issues in Digital VLSI Circuits and Systems; A Special Issue of A Juan J. Becerra,Eby G. Friedman Book 1997 Springer Science+

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Design and Evaluation of Adiabatic Arithmetic Unitsiabatic designs, and present the findings of our empirical comparison. Our results suggest that adiabatic logic can be used for the implementation of relatively complex VLSI circuits that dissipate significantly less energy than their corresponding CMOS designs.

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Analysis of Metastable Operation in a CMOS Dynamic D-Latched through electric simulation with HSPICE. After that, we have compared the metastable behavior of the dynamic latch with its static counterpart, obtaining results about the characteristic parameters of metastability and the Mean Time Between Failures (MTBF) for both kinds of bistable circuits. The

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Selection of Voltage Thresholds for Delay Measurementdigital abstraction is done. This delay should be positive and non-zero, since a physical device takes a finite amount of time to respond to the input. Defining a strictly positive delay is not a problem in the abstract domain of logic signals, since input and output “events” are precisely defined.

Cryptic

Delay and Power Expressions for a CMOS Inverter Driving a Resistive-Capacitive Loadxhibits good accuracy. The model can be used to design and analyze those CMOS inverters that drive a large RC load when considering both speed and power. Expressions are provided for estimating the propagation delay and transition time which exhibit less than 27% discrepancy from SPICE for a wide va

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Design and Evaluation of Adiabatic Arithmetic Unitsg techniques. Despite the plethora of adiabatic logic architectures that have been proposed in recent years, several practical considerations in the design of nontrivial adiabatic circuits remain largely unexplored. Moreover, it is still unclear whether adiabatic circuits of significant size and com