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Titlebook: Advances in Communication, Signal Processing, VLSI, and Embedded Systems; Select Proceedings o Shubhakar Kalya,Muralidhar Kulkarni,K.S. Shi

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樓主: mortality
41#
發(fā)表于 2025-3-28 17:38:58 | 只看該作者
42#
發(fā)表于 2025-3-28 19:55:07 | 只看該作者
https://doi.org/10.1007/978-981-15-0626-0Neural Networks; Image Enhancement; Convolutional Neural Networks; Image Fusion; Bio Sensors; Underwater
43#
發(fā)表于 2025-3-29 00:44:30 | 只看該作者
978-981-15-0628-4Springer Nature Singapore Pte Ltd. 2020
44#
發(fā)表于 2025-3-29 03:06:01 | 只看該作者
Advances in Communication, Signal Processing, VLSI, and Embedded Systems978-981-15-0626-0Series ISSN 1876-1100 Series E-ISSN 1876-1119
45#
發(fā)表于 2025-3-29 11:11:46 | 只看該作者
Diogo R. Ferreira,Rui M. Santos results in very low-power consumption. In this paper, active high-pass filters are designed which operates at low voltage and also has very low-power consumption. The filters are designed in Cadence Virtuoso tool using 180?nm CMOS technology at the supply of 1.6?V. Gain and cut-off frequency of the designed filters are determined.
46#
發(fā)表于 2025-3-29 12:35:19 | 只看該作者
Business Process Management Workshopsters suffer from errors caused due to accelerations that add to gravity. This makes the position obtained from accelerometers unreliable and inaccurate. Gyroscopes are encountered by data drifting problems. This paper illustrates pose estimation by integrating the IMU data. A moving average filter i
47#
發(fā)表于 2025-3-29 17:40:14 | 只看該作者
Fernanda Gonzalez-Lopez,Guillermo Bustosrket and design efforts, reusable, pretested modules called intellectual properties (IPs) are incorporated in the design. Hence, designing mainly relies on interconnection of modules that may lead to unintentional functional paths. As SoC may contain several secure and non-secure modules, data propa
48#
發(fā)表于 2025-3-29 21:10:24 | 只看該作者
49#
發(fā)表于 2025-3-30 01:38:43 | 只看該作者
Diogo R. Ferreira,Rui M. Santos results in very low-power consumption. In this paper, active high-pass filters are designed which operates at low voltage and also has very low-power consumption. The filters are designed in Cadence Virtuoso tool using 180?nm CMOS technology at the supply of 1.6?V. Gain and cut-off frequency of the
50#
發(fā)表于 2025-3-30 05:44:40 | 只看該作者
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